1. Field of the Invention
The present invention relates to power supply circuits and more particularly to power supply circuits such as synchronous rectifier type power supply circuits in which reduction of a through current is intended.
2. Prior Art
In recent years, mobile apparatuses such as cellular phones have been widely used, so that it is more frequent that batteries are used to drive a circuit serving as a load. Accordingly, it is essential that power consumption of the power supply circuits be of a small volume. Moreover, it is also necessary that the power supply circuits are capable of speedily responding to load variations.
It will be required to provide stabilized direct-current power supplies using low voltage with low power consumption as electronic apparatuses using integrated circuits become more popular.
A power supply is stabilized by the switching operation of turning “on” and “off” a transistor in accordance with changes in the load and an input, such that wasteful consumption of power can be restrained. Consequently, the efficiency of the power supply can be very much enhanced. In other words, the power supply can be stabilized by varying an “on” period (or an on-duty) of the transistor. Such efficient power supply circuits include synchronous rectifier type switching regulators using complementary metal oxide semiconductor (CMOS) integrated circuits.
The configuration of the CMOS integrated circuit employs a combination of two kinds of metal oxide semiconductor transistors, an N channel transistor (hereinafter abbreviated as NMOS) and a P channel transistor (hereinafter abbreviated as PMOS). Because of its characteristic of low power consumption, the CMOS integrated circuit is a mainstream of the large scale integration technology.
FIG. 13 shows a configuration of a synchronous rectifier type-switching regulator using a CMOS integrated circuit.
In FIG. 13, the configuration of the power supply circuit includes a synchronous rectifier type switching regulator circuit with a high-side PMOS (hereinafter referred to as high side transistor) (QP1) and a low-side transistor (hereinafter referred to as low side transistor) (QN1), for outputting a direct current voltage VOUT, which is a DC voltage and an alternate current voltage, by alternately turning “on” and “off” the transistors. The circuit also includes an error amplifier 40 for producing an error signal by comparing an output voltage of the switching regulator circuit to a reference voltage value of a reference voltage supply E; a Pulse Width Modulation (PWM) circuit 32 for controlling the output of the switching regulator circuit to be constant by controlling the pulse width of a PWM signal based on the error signal; and an output driver 31 for receiving an input of the PWM signal of the PWM circuit 32 and forming gate pulses SH and SL to be supplied to the high side transistor (QP1) and the low side transistor (QN1), respectively, of the switching regulator circuit. Here, the PWM circuit 32 and the output driver 31 form a PWM means.
The switching regulator circuit is configured such that the high side transistor (QP1) and the low side transistor (QN1) are connected in series, having a drain D in common between a terminal 1 to which direct current voltage VIN (=power supply voltage VDD, for example, 4V), i.e. an input voltage, is supplied and a terminal 2 to which a reference potential VSS (=ground potential GND, for example, 0V) is supplied. A source S of the high side transistor (QP1) is connected to the terminal 1 while a source S of the low side transistor (QN1) is connected to the terminal 2.
High-frequency pulses SH and SL as PWM signals are supplied to the gates of the high side transistor (QP1) and the low side transistor (QN1) from the PWM means, respectively, and, the transistors are alternately turned “on”/“off” by the high-frequency pulses SH and SL. Consequently, an alternate current voltage VMA is generated at an intermediate node K which is the junction point of the both transistors.
A rectifier coil L1 and a stabilizing capacitance C0 are connected in series between the intermediate node K where the alternate current voltage VMA is generated and a terminal 2 to which the reference potential VSS is supplied. The direct current voltage VOUT (for example, 1.5V) smoothed by the stabilizing capacitance C0 is output to an output terminal 4 connected to the junction point of the series connection so as to be supplied to a load not illustrated in the drawing.
Then, the output direct current voltage VOUT is returned to one terminal of the error amplifier 40 through a feedback line and then compared with the reference voltage value of the reference voltage supply E connected to a terminal 5 to which the reference potential VSS is supplied.
The error voltage, which is the comparison result produced by the error amplifier 40, is supplied to the PWM circuit 32, and the pulse width of the PWM signal generated by the PWM circuit 32 is controlled by the error voltage. Here, the PWM signal output from the PWM circuit 32 and the gate pulse SH as the PWM signal output from the output driver 31 are inversely related.
Regarding the control of the high-side transistor (QP1) and the low-side transistor (QN1), which are connected in series between the power supply voltage VIN and the reference potential VSS as described above, it is necessary to control turning “on” one of the above transistors always after the other transistor is turned “off”. Otherwise, a through current would run between the transistors, thereby remarkably deteriorating the efficiency.
FIG. 14 shows a circuit diagram illustrating an example of a configuration of the above output driver 31.
In FIG. 14, the configuration of the output driver 31 includes an input terminal 6 to which the PWM signal from the PWM circuit 32 is input; an inverter 311; a two-input NAND gate 312; inverters 313 and 314; a two-input NAND gate 315; inverters 316 and 317; an output terminal 9 that outputs the high-frequency pulse SH which will be the gate signal of the high side transistor (QP1); and an output terminal 10 that outputs the high-frequency pulse SL which will be the gate signal of the low side transistor (QN1).
According to this logic structure, when the PWM signal input to the input terminal 6 is low, the SH signal of the output terminal 9 is high, two inputs of the two-input NAND gate 315 are both high, and the SL signal of the output terminal 10 is high. Moreover, when the PWM signal input to the input terminal 6 is high, the output of the two-input NAND gate 315 is high and the SL signal of the output terminal 10 is low while two inputs to the two-input NAND gate 312 are both high and the SH signal of the output terminal 9 is low. The output driver 31 with the above configuration employs a so called ‘cross’ logic style. This ‘cross’ logic prevents the high side transistor (QP1) and the low side transistor (QN1), which are connected in series between the power supply voltage and the reference potential, from turning “on” simultaneously caused by the time delay between logic elements. Hence, a through current is prevented from running between the transistors.
However, with the structure of the output driver shown in FIG. 14, it has been difficult to prevent the through current from running from the high-side to the low-side due to the gate capacities and the speed of response of power MOS transistors constituting the high side and the low side transistor. Namely, it has been difficult to eliminate the through current depending on the characteristic and the type of power MOS transistor.
In light of the above problem, the present invention aims to provide a power supply circuit capable of preventing the through current and enhancing the conversion efficiency.